I have always wanted to tell you about the theory of ESD, it is very classic. However, because it is too theoretical, if you don’t understand the previous device theory and snap-back theory, don’t waste your time reading this. Any theory is linked to each other. If you can’t draw an egg, you are destined to not be able to draw David.

 

      Electrostatic discharge (ESD: Electrostatic Discharge) should be the main culprit that causes excessive electrical stress (EOS: Electrical Over Stress) damage to all electronic components or integrated circuit systems. Because static electricity usually has a very high instantaneous voltage (> several thousand volts), this damage is devastating and permanent, causing the circuit to burn directly. Therefore, preventing electrostatic damage is the number one problem in all IC design and manufacturing.

 

      Static electricity is usually man-made. During processes such as production, assembly, testing, storage, and transportation, static electricity may accumulate in the human body, instruments, or equipment. Even the components themselves may accumulate static electricity. When people do not know it, When these charged objects come into contact, a discharge path will be formed, which will instantly cause electronic components or systems to be damaged by electrostatic discharge (this is why in the past, when repairing computers, one had to wear an electrostatic ring on the work table to prevent human body damage. Static electricity damages the chip), just like the charge stored in the clouds instantly breaks through the clouds to produce violent lightning, which will split the earth. And it usually happens when rainy days come, because the air humidity is easy to form conductive paths.

 

       So, how to prevent electrostatic discharge damage? First of all, of course, change the environment to reduce static electricity from the source (such as reducing friction, wearing less woolen sweaters, controlling air temperature and humidity, etc.). Of course, this is not the focus of our discussion today. What we are going to discuss today is how to include a protection circuit in the circuit. When there is static electricity outside, our electronic components or systems can protect themselves from being damaged by static electricity (actually, installing a lightning rod). This is also the number one problem for many IC designers and manufacturers. Many companies have teams specializing in ESD design. Today I will start with the most basic theory and gradually explain the principles and precautions of ESD protection. You will find that the PN mentioned earlier Junction/diodes, transistors, MOS tubes, and snap-backs are all used. . .

 

       When the previous topic explained the theory of PN junction diodes, we mentioned that diodes have a characteristic: forward conduction and reverse interception (if you don’t remember, go to the previous course), and if the reverse bias voltage continues to increase, avalanche breakdown will occur. ) and conduct, we call it a clamping diode (Clamp). This is exactly the theoretical basis we need to design electrostatic protection. We use this reverse cut-off characteristic to keep the bypass in a disconnected state during normal operation. When there is static electricity outside, the bypass diode undergoes avalanche breakdown. The bypass path protects the internal circuit or grid (is it similar to the overflow opening in the sink at home to prevent the faucet from being turned off and causing flooding in the entire bathroom). So the question is, if the protection circuit is broken down, will it be completely dead? Is it a one-time thing? The answer is of course not. There are two types of breakdown of PN junction, namely electrical breakdown and thermal breakdown. Electric breakdown refers to avalanche breakdown (low concentration) and Zener breakdown (high concentration), and this electrical breakdown is mainly caused by load. Streamer collision ionization generates new electron-hole pairs (electron-holes), so it is recoverable. However, thermal breakdown is irrecoverable because the heat accumulation causes the silicon (Si) to be melted and burned. Therefore, we need to control the current at the moment of conduction. Generally, a high resistor is connected in series with the protection diode. In addition, can you draw inferences to understand why the ESD area cannot form Silicide? Let me give you a theory. ESD is usually located next to the pad at the input end of the chip, not inside the chip, because we always hope that the static electricity from the outside needs to be discharged as soon as possible. There will be a delay if placed inside (follow me There are diodes next to the chip PAD dissected earlier http://ic-garden.cn/?p=482). There are even two levels of ESD to achieve double protection.

 

      Before talking about the principles and processes of ESD, let us first talk about the standards and testing methods of ESD. According to the way static electricity is generated and the damage mode to the circuit, it is usually divided into four testing methods: Human-Body Model (HBM: Human-Body Model) ), machine discharge mode (Machine Model), component charging mode (CDM: Charge-Device Model), and electric field induction mode (FIM: Field-Induced Model), but the industry usually uses the first two modes for testing (HBM, MM).

 

        1. Human body discharge model (HBM): Of course, the charge generated by human body friction suddenly hits the charge released by the chip, causing the chip to burn down and breakdown. This is the reason why you often get electric shock when you come into contact with others in autumn. The industry also has traces of HBM's ESD standards (MIL-STD-883C method 3015.7, equivalent human body capacitance is 100pF, equivalent human body resistance is 1.5Kohm), or the international electronic industry standard (EIA/JESD22-A114-A) It’s stipulated, it depends on which one you want to follow. If it is MIL-STD-883C method 3015.7, it stipulates that those less than <2kV are Class-1, those between 2kV~4kV are Class-2, and those between 4kV~16kV are Class-3.

 

        2. Machine discharge mode (MM): Of course, the static electricity generated by the movement of the machine (such as a robot) is released by the pin when it touches the chip. The sub-standard is EIAJ-IC-121 method 20 (or standard EIA/JESD22-A115-A) , the equivalent machine resistance is 0 (because of the metal), and the capacitance is still 100pF. Since the machine is metal and the resistance is 0, the discharge time is very short, almost between ms or us. But the more important problem is that since the equivalent resistance is 0, the current is very large, so even a 200V MM discharge is more harmful than a 2kV HBM discharge. Moreover, the machine itself has many wires that couple to each other, so the current will interfere with changes over time.

 

 

    The ESD test method is similar to the GOI test in FAB. After specifying the pin, give it an ESD voltage for a period of time, then come back and test the electrical properties to see if it is damaged. If there is no problem, add another step of ESD voltage and continue for a period of time. time, and then measure the electrical properties, and repeat this until breakdown. The breakdown voltage at this time is the critical voltage of ESD breakdown (ESD failure threshold Voltage). Usually we apply voltage to the circuit three times (3 zaps). In order to reduce the test cycle, the starting voltage is usually 70% of the ESD threshold of the standard voltage. Each step can be adjusted to 50V or 100V as needed.

 

 

(1). Stress number = 3 Zaps. (5 Zaps, the worst case)
(2). Stress step	ΔVESD = 50V(100V) for VZAP <=1000V ΔVESD = 100V(250V, 500V) for VZAP > 1000V
(3). Starting VZAP = 70% of averaged ESD failure threshold (VESD)

      In addition, because each chip has many pins, whether you test the pins one by one or in combination, it will be divided into several combinations: I/O-pin test (Input and Output pins), pin-to-pin test, Vdd-Vss test (input to output), Analog-pin.

 

       1. I/O pins: ESD tests are performed on input-pin and output-pin respectively, and the charges are divided into positive and negative, so there are four combinations: input+positive charge, input+negative charge, output+positive charge, output+negative charge . When testing the input, the output and other pins are all floating, and vice versa.

 

     2. Pin-to-pin test: Electrostatic discharge occurs between pin-to-pin to form a loop, but if you want to test every two pins in too many combinations, because any I/O will give voltage to the entire circuit. The impact must first go through VDD/Vss before powering the entire circuit, so the improved version uses a certain I/O-pin to add positive or negative ESD voltage, and all other I/Os are grounded together, but the input and output are floating at the same time ( Floating).

 

     3. Electrostatic discharge between Vdd-Vss: Just connect Vdd and Vss, and all I/Os are floating, so that static electricity can pass between Vdd and Vss.

 

      4. Analog-pin discharge test: Because many differential pairs (Differential Pairs) or operational amplifiers (OP AMP) in analog circuits have two input terminals, to prevent one damage from causing the differential comparison or operation to fail, ESD needs to be done separately. The test, of course, is only for these two pins, and all other pins are floating.

 

Okay, that’s it for the principles and testing of ESD. Now let’s talk about Process and design factors.

 

     As Moore's Law further shrinks, the device size becomes smaller and smaller, the junction depth becomes shallower and shallower, and GOX becomes thinner and thinner, so electrostatic breakdown becomes easier and easier. Moreover, in the Advance process, the introduction of Silicide will also cause electrostatic breakdown. It becomes sharper, so almost all chip designs have to overcome the problem of electrostatic breakdown.

 

     Electrostatic discharge protection can be solved from the Process on the FAB side, or it can be designed from the Layout on the IC design side, so you will see that Process has an ESD option layer, or there are ESD design rules in the Design rule for customers to choose, etc. Of course, some customers will also design ESD through layout based on the electrical properties of the SPICE model.

 

      1. ESD in the manufacturing process: Either change the PN junction or change the load resistance of the PN junction. Changing the PN junction can only rely on ESD_IMP. To change the load resistance of the PN junction, use non-silicide or series resistance. .

 

          1) Source/Drain’s ESD implant: Because our LDD structure can easily form two shallow junctions on both sides of the gate poly, and the sharp electric field of this shallow junction is relatively concentrated, and because it is a shallow junction, it is relatively close to the Gate. Therefore, it is greatly affected by the electric field at the end of the Gate, so the ability of such LDD sharp corners to withstand ESD discharge is relatively poor (<1kV), so if such a Device is used in an I/O port, it is easy to cause ESD damage. So according to this theory, we need a separate device without LDD, but we need another ESD implant to make a deeper N+_S/D, so that the sharp corners can be rounded and far away from the surface, so it can be obviously Improve ESD breakdown capability (>4kV). But in this case, the Gate of this additional MOS must be very long to prevent punchthrough, and because the devices are different, the SPICE Model of the device needs to be extracted separately.

 

            2) ESD implant of contact hole: Drill a P+ boron under the N+ drain hole of the LDD device, and the depth should exceed the depth of the N+ drain (drain), so that the breakdown voltage of the original drain can be increased Reduced (8V-->6V), so it can be conducted away from the Drain breakdown before the LDD sharp corner breakdown occurs to protect the Drain and Gate breakdown. Therefore, this design can keep the device size unchanged and the MOS structure does not change, so there is no need to re-extract the SPICE model. Of course, this kind of intelligence is used in non-silicide processes, otherwise you won’t be able to make contact and implant.

 

            3) SAB (SAlicide Block): Generally, in order to reduce the interconnection capacitance of MOS, we will use the silicide/SAlicide process. However, if the device works at the output end, the load resistance of our device will become lower, and the external ESD voltage will be fully loaded. It is easy to break down between the LDD and Gate structures, so for the Silicide/Salicide of the MOS in the output stage, we usually use a SAB (SAlicide Block) mask to block the RPO, so as not to form a silicide. Adding a photo layer increases the cost, but ESD The voltage can be increased from 1kV to 4kV.

 

              4) Series resistance method: This method does not need to add a photomask and should be the most economical. The principle is somewhat similar to the third (SAB) method of adding resistance. I deliberately connected a resistor in series with it (such as Rs_NW, or HiR, etc.), this also achieves the SAB method.

 

       2. ESD in design: This completely depends on the designer's efforts. Some companies have already provided solutions to customers in the design rules. Customers only need to follow the drawings. Some companies do not have to rely on the customer's own designer. , many design rules state that this is just a guideline/reference, not a guarantee. Generally, the Gate/Source/Bulk are short-circuited together, and the Drain junction is placed at the I/O end to withstand the ESD surge voltage. NMOS is called GGNM.OS (Gate-Grounded NMOS), PMOS is called GDPMOS (Gate-to-Drain PMOS).

 

       Taking NMOS as an example, the principle is that the gate is closed. The PN junction of Source/Bulk is originally short-circuited to 0 bias. When there is a large voltage at the I/O terminal, the Drain/Bulk PN junction undergoes avalanche breakdown, and the bulk instantly has a large voltage. The voltage difference between the current and the substrate resistance causes the PN of Bulk/Source to be forward biased, so the parasitic lateral NPN tube of this MOS enters the amplification area (the emitter junction is forward biased and the collector junction is reverse biased), so it exhibits Snap-Back characteristics, which plays a role Protective effects. PMOS is derived in the same way.

 

       This principle seems simple, but what is the essence of design (know-how)? How to trigger BJT? How to maintain Snap-back? How to support HBM>2KV or 4KV?

 

       How to trigger? There must be a large enough substrate current, so the multi-finger parallel structure (multi-finger) that is now commonly used was later developed. However, the main technical problem with this structure is that the width of the base area increases and the amplification factor decreases, so Snap-back is not easy to turn on. And as the number of fingers increases, it will become difficult to turn on each finger evenly, which is also the bottleneck of ESD design.

 

        If you want to change this problem, there are probably two methods (because the triger is voltage, and improving the voltage is either resistance or current): 1. Use SAB (SAlicide-Block) to form a high-resistance on the I/O drain. The non-Silicide area increases the drain block resistance, making the ESD current distribution more uniform, thereby improving the discharge capability; 2. Add a P-ESD (Inner-Pickup imp, similar to the contact hole P+ ESD imp above), Put a P+ under N+Drain to reduce the avalanche breakdown voltage of Drain and have more avalanche breakdown current earlier (see the literature paper: Inner Pickup on ESD of multi-finger NMOS.pdf for details).

 

        There are two little common senses that I would like to share with you about Snap-back ESD:

 

           1) We can usually see better Snap-back characteristics in NMOS, but in fact it is difficult for PMOS to have snap-back characteristics, and PMOS generally has better ESD resistance than NMOS. This is the same as the HCI effect, mainly because of the NMOS Electrons are generated during breakdown, and their mobility is very high, so it is easy to make Bulk/Source forward conductive if Isub is large, but it is difficult for PMOS.

 

         2) Trigger voltage/Hold voltage: The Trigger voltage is of course the first inflection point (Knee-point) of the previously mentioned snap-back, the breakdown voltage of the parasitic BJT, and it must be between BVCEO and BVCBO. The Hold voltage is to keep the Snap-back ON, but it cannot enter the latch-up state, otherwise it will enter a secondary breakdown (thermal breakdown) and be damaged. Another concept is the secondary breakdown current. After entering the Latch-up, the I^2*R heat increases suddenly and causes the silicon to melt. This is to limit the current. You can control W/L or add a high current limit. The simplest and most commonly used method is to increase the Drain distance/increase the SAB distance (a common practice in ESD rules).

 

 

     3. Gate-Couple ESD technology: As we just said, the bottleneck of Multi-finger ESD design is the uniformity of opening. Assume that there are 10 fingers. When ESD discharge occurs, these 10 fingers are not They may not all be turned on at the same time (usually due to Breakdown). It is common that only 2-3 fingers will be turned on first. This is because the layout cannot make the relative position and wire pulling direction of each finger exactly the same. These two Once ~3 fingers are turned on, the ESD current will flow concentratedly to these 2~3 fingers, while the other fingers remain closed, so its ESD protection capability is equivalent to the protection capability of only 2~3 fingers. Not the protective capability of 10 fingers. This is the main reason why the component size has been made larger, but the ESD protection capability has not increased as expected. The increase in area has not brought about ESD enhancement as expected. What should I do? In fact, it is very simple, that is, to reduce Vt1 (Trigger voltage), we increase the voltage through the gate, so that the substrate turns on first instead of breakdown and conducts in advance to generate substrate current. At this time, other fingers can also turn on and enter. The conductive state allows each finger to withstand ESD current and truly exert a large-area ESD effect.

 

      However, one disadvantage of this GCNMOS ESD design is that when the channel is turned on, a current is generated that easily causes gate oxide breakdown. Therefore, it is not a good ESD design solution, and the smaller the active area, the greater the impact of the gate voltage. The larger the active area is, the harder it is to turn on the snap-back, so it is difficult to grasp.

 

 

      4. There is also a complex ESD protection circuit: Silicon Controlled Rectifier (SCR: Silicon Controlled Rectifier), which is the CMOS parasitic PNPN structure we talked about before that triggers Snap-Back and Latch-up, and is realized through ON/OFF For circuit protection, you can review it. Just use the factors that suppress LATCH-up in the previous article and let it happen. However, it can only be applied to Layout, not Process, otherwise Latch-up will fail again. .
 

      Finally, the knowledge of ESD design is too deep. I am just here to introduce some ideas to FAB people to popularize the science. Basically, there are the following ESD solutions: resistor voltage divider, diode, MOS, parasitic BJT, SCR (PNPN structure), etc. method. Moreover, ESD is not only related to Design, but also related to FAB process. The knowledge is too deep and I don’t understand it very well.