Via (via) is one of the important components of multi-layer PCB. The cost of drilling usually accounts for 30% to 40% of the PCB board manufacturing cost. Simply put, every hole on the PCB can be called a via. In terms of function, vias can be divided into two categories:

One is used as electrical connection between layers;

The second is used for fixing or positioning the device.

From a process perspective, these vias are generally divided into three categories, namely blind vias, buried vias and through vias. Blind holes are located on the top and bottom surfaces of the printed circuit board and have a certain depth. They are used to connect the surface circuits and the inner circuits below. The depth of the holes usually does not exceed a certain ratio (aperture). Buried vias refer to connection holes located on the inner layer of a printed circuit board and do not extend to the surface of the circuit board. The above two types of holes are located in the inner layer of the circuit board. They are completed using the through-hole forming process before lamination. During the via-hole formation process, several inner layers may be overlapped. The third type is called a through hole, which passes through the entire circuit board and can be used to implement internal interconnections or as mounting positioning holes for components. Because through holes are easier to implement in technology and have lower costs, most printed circuit boards use them instead of the other two via holes. The vias mentioned below are considered as through holes unless otherwise specified.

 

From a design point of view, a via hole mainly consists of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole, as shown in the figure below. The size of these two parts determines the size of the via hole. Obviously, when designing high-speed, high-density PCBs, designers always hope that the vias should be as small as possible, so that more wiring space can be left on the board. In addition, the smaller the vias, the smaller their own parasitic capacitance. The smaller it is, the more suitable it is for high-speed circuits. However, the reduction in hole size also brings

Due to the increase in cost, the size of the via hole cannot be reduced indefinitely. It is limited by process technologies such as drilling and plating: the smaller the hole, the longer it takes to drill, and The easier it is to deviate from the center position; and when the depth of the hole exceeds 6 times the diameter of the drilled hole, there is no guarantee that the hole wall can be plated with copper evenly. For example, the current normal thickness (through hole depth) of a 6-layer PCB board is about 50 Mil, so the minimum drilling diameter that the PCB manufacturer can provide can only reach 8 Mil.

 

2. Parasitic capacitance of vias

The via itself has a parasitic capacitance to ground. If it is known that the diameter of the isolation hole on the ground layer is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the board substrate is ε, then the parasitic capacitance of the via is approximately: C=1.41εTD1/(D2-D1)

The main impact of the parasitic capacitance of the via on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit. For example, for a PCB board with a thickness of 50 Mil, if a via hole with an inner diameter of 10 Mil and a pad diameter of 20 Mil is used, and the distance between the pad and the ground copper area is 32 Mil, we can approximately calculate the via hole through the above formula The parasitic capacitance is roughly: C=1.41x4.4x0.050x0.020/(0.032-0.020)=0.517pF. The change in rise time caused by this part of the capacitance

It is: T10-90=2.2C(Z0/2)=2.2x0.517x(55/2)=31.28ps. It can be seen from these values that although the effect of slowing down the rise delay caused by the parasitic capacitance of a single via is not very obvious, designers should still consider it carefully if vias are used multiple times in the wiring for switching between layers.

 

3. Parasitic inductance of vias

Similarly, there are parasitic capacitances in vias and parasitic inductances. In the design of high-speed digital circuits, the harm caused by the parasitic inductance of vias is often greater than the influence of parasitic capacitance. Its parasitic series inductance will weaken the contribution of the bypass capacitor and weaken the filtering effect of the entire power system. We can use the following formula to simply calculate the approximate parasitic inductance of a via: L=5.08h[ln(4h/d)+1] where L refers to the inductance of the via, h is the length of the via, and d is the center The diameter of the drilled hole. It can be seen from the formula that the diameter of the via hole has a small impact on the inductance, but the length of the via hole has the greatest impact on the inductance. Still using the above example, the inductance of the via can be calculated as: L=5.08x0.050[ln(4x0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance is: XL=πL/T10-90=3.19Ω. Such impedance cannot be ignored when high-frequency current flows through it. Special attention should be paid to the fact that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer, so the parasitic inductance of the vias will increase exponentially.

 

4. Via design in high-speed PCB

Through the above analysis of the parasitic characteristics of vias, we can see that in high-speed PCB design, seemingly simple vias often bring great negative effects to the circuit design. In order to reduce the adverse effects caused by the parasitic effects of vias, try to do the following in the design:

1. Consider both cost and signal quality, and select a reasonably sized via size. For example, for 6-10-layer memory module PCB design, it is better to use 10/20Mil (drilling/pad) vias. For some high-density, small-size boards, you can also try to use 8/18Mil vias. hole. Under current technical conditions, it is difficult to use smaller-sized vias. For power or ground vias, consider using larger sizes to reduce impedance.

2. From the two formulas discussed above, it can be concluded that using a thinner PCB board is beneficial to reducing the two parasitic parameters of the vias.

3. Try not to change layers of signal traces on the PCB board, that is to say, try not to use unnecessary vias.

4. The power and ground pins should be drilled nearby. The shorter the leads between the vias and the pins, the better, because they will

causing an increase in inductance. At the same time, the power and ground leads should be as thick as possible to reduce impedance.

5. Place some grounded vias near the vias of the signal layer to provide the nearest loop for the signal. You can even place a large number of redundant ground vias on the PCB board. Of course, you also need to be flexible in your design. The via model discussed earlier is a case where each layer has a pad. Sometimes, we can reduce or even remove the pads on some layers. Especially when the via hole density is very high, it may cause a broken groove to be formed in the copper layer to isolate the circuit. To solve this problem,

Question In addition to moving the position of the via hole, we can also consider reducing the pad size of the via hole in the copper layer.